Represents a crystal clock signal generator. Number of electrodes can be specified. 表示晶体时钟信号发生器。可指定电极数目。
The first, we analyze the system operation theory of CMOS image sensor with pixel level ADC ( A/ D Converter). It is made up of three sections: pixel array, clock signal generator and SAM ( Sequential Access Memory). 首先,我们对像素级A/D转换型图像传感器的系统工作原理进行了分析,是由像素阵列、时钟信号产生器和SAM(顺序读写存储器)三部分构成的。
Besides, we can improve system performance by increasing clock frequency and selecting high efficient component, and realize high frequency signal generator and various waveform signal generator. 另外,通过提高时钟频率,并有效地选择高效率的相关器件,我们还能够对该设备进行进一步的完善和改进,从而实现高频率的信号发生器及任意波形信号发生器。
The scheme of external clock frequency multiplying and measures for preventing clock leakage are adopted in DDS signal generator, thus featuring better spurious and noise characteristic. 该设计在DDS信号产生部分运用外部时钟倍乘方式和防止时钟泄漏等措施,获得了更好的杂散与噪声特性;
The HDB3 coding circuit and clock-and-enabling signal generator are discussed in particular. 并详细分析了HDB3码变换电路和时钟/使能信号产生单元的设计过程。
Direct Digital Synthesize ( DDS) is used to generate clock signal at any frequency so that data generator can output data at any rate. 着重分析采用直接数字合成(DDS)技术产生任意频率时钟信号的方法,实现数据发生器以任意码率输出数据;
The effect of time-delay precision on the beamforming performance is also analyzed, and it is shown that when the clock frequency is high enough, it is feasible to combine multiple D flip-flop loops of different clock sources into a signal generator of even more channels. 论文还分析了信号延时精度对波束形成性能的影响,论证了时钟频率足够高时,把使用不同时钟源的多个D触发器环路合成具有更多通道数的装置是可行的。
Circuit-level specifications were determined for circuit design., Furthermore, designs of various unit circuits in the Sigma-Delta modulator, including the switch-capacitor integrator, the comparator, the single-bit DAC and the non-overlapped clock signal generator, were completed at the transistor-level. 在此基础上,对Sigma-Delta调制器的各个单元电路进行了晶体管级设计,包括开关电容积分器、比较器、一位DAC和非交叠时钟信号产生电路等。